/* Date Stamp: 8/23/2014 */

#ifndef IIO_IOAPIC_h
#define IIO_IOAPIC_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_IOAPIC_DEV 5                                                           */
/* IIO_IOAPIC_FUN 4                                                           */

/* VID_IIO_IOAPIC_REG supported on:                                           */
/*       IVT_EP (0x2002C000)                                                  */
/*       IVT_EX (0x2002C000)                                                  */
/*       HSX (0x2002C000)                                                     */
/*       BDX (0x2002C000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_IOAPIC_REG 0x09042000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_IOAPIC_REG supported on:                                           */
/*       IVT_EP (0x2002C002)                                                  */
/*       IVT_EX (0x2002C002)                                                  */
/*       HSX (0x2002C002)                                                     */
/*       BDX (0x2002C002)                                                     */
/* Register default value on IVT_EP:    0x0E2C                                */
/* Register default value on IVT_EX:    0x0E2C                                */
/* Register default value on HSX:       0x2F2C                                */
/* Register default value on BDX:       0x6F2C                                */
#define DID_IIO_IOAPIC_REG 0x09042002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100101100 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel QPI
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x2002C004)                                                  */
/*       IVT_EX (0x2002C004)                                                  */
/*       HSX (0x2002C004)                                                     */
/*       BDX (0x2002C004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_IOAPIC_REG 0x09042004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RW, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RW, default = 1'b0 
       1
     */
    UINT16 spcen : 1;
    /* spcen - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 memwrinv : 1;
    /* memwrinv - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga : 1;
    /* vga - Bits[5:5], RO, default = 1'b0 
       1
     */
    UINT16 perrrsp : 1;
    /* perrrsp - Bits[6:6], RO, default = 1'b0 
       1
     */
    UINT16 idsel : 1;
    /* idsel - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 fb2be : 1;
    /* fb2be - Bits[9:9], RO, default = 1'b0 
       1
     */
    UINT16 intxdisable : 1;
    /* intxdisable - Bits[10:10], RO, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x2002C006)                                                  */
/*       IVT_EX (0x2002C006)                                                  */
/*       HSX (0x2002C006)                                                     */
/*       BDX (0x2002C006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_IOAPIC_REG 0x09042006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxst : 1;
    /* intxst - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 sixtysixmhzcap : 1;
    /* sixtysixmhzcap - Bits[5:5], RO, default = 1'b0 
       1
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fb2bcap : 1;
    /* fb2bcap - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 medierr : 1;
    /* medierr - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 devselt : 2;
    /* devselt - Bits[10:9], RO, default = 2'b00 
       1
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RW1C, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RO_V, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_IOAPIC_REG supported on:                                           */
/*       IVT_EP (0x1002C008)                                                  */
/*       IVT_EX (0x1002C008)                                                  */
/*       HSX (0x1002C008)                                                     */
/*       BDX (0x1002C008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_IOAPIC_REG 0x09041008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x1002C009)                                                  */
/*       IVT_EX (0x1002C009)                                                  */
/*       HSX (0x1002C009)                                                     */
/*       BDX (0x1002C009)                                                     */
/* Register default value on IVT_EP:    0x20                                  */
/* Register default value on IVT_EX:    0x20                                  */
/* Register default value on HSX:       0x00                                  */
/* Register default value on BDX:       0x00                                  */
#define CCR_N0_IIO_IOAPIC_REG 0x09041009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.4.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_IOAPIC_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x2002C00A)                                                  */
/*       IVT_EX (0x2002C00A)                                                  */
/*       HSX (0x2002C00A)                                                     */
/*       BDX (0x2002C00A)                                                     */
/* Register default value on IVT_EP:    0x0800                                */
/* Register default value on IVT_EX:    0x0800                                */
/* Register default value on HSX:       0x0800                                */
/* Register default value on BDX:       0x0880                                */
#define CCR_N1_IIO_IOAPIC_REG 0x0904200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_IOAPIC_REG supported on:                                          */
/*       IVT_EP (0x1002C00C)                                                  */
/*       IVT_EX (0x1002C00C)                                                  */
/*       HSX (0x1002C00C)                                                     */
/*       BDX (0x1002C00C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_IOAPIC_REG 0x0904100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x00c
 */
typedef union {
  struct {
    UINT8 clsr_reg : 8;
    /* clsr_reg - Bits[7:0], RW, default = 8'b00000000 
       1
     */
  } Bits;
  UINT8 Data;
} CLSR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_IOAPIC_REG supported on:                                           */
/*       IVT_EP (0x1002C00E)                                                  */
/*       IVT_EX (0x1002C00E)                                                  */
/*       HSX (0x1002C00E)                                                     */
/*       BDX (0x1002C00E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_IOAPIC_REG 0x0904100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* MBAR_IIO_IOAPIC_REG supported on:                                          */
/*       IVT_EP (0x4002C010)                                                  */
/*       IVT_EX (0x4002C010)                                                  */
/*       HSX (0x4002C010)                                                     */
/*       BDX (0x4002C010)                                                     */
/* Register default value:              0x00000000                            */
#define MBAR_IIO_IOAPIC_REG 0x09044010
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x010
 */
typedef union {
  struct {
    UINT32 memory_space : 1;
    /* memory_space - Bits[0:0], RO, default = 1'b0 
       This Base Address Register indicates memory space.
     */
    UINT32 type : 2;
    /* type - Bits[2:1], RO, default = 2'b00 
       The IOAPIC registers can only be placed below 4G system address space.
     */
    UINT32 prefetchable : 1;
    /* prefetchable - Bits[3:3], RO, default = 1'b0 
       The IOxAPIC registers are not prefetchable.
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[11:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 bar : 20;
    /* bar - Bits[31:12], RW, default = 20'b00000000000000000000 
       This marks the 4KB aligned 32-bit base address for memory-mapped registers of 
       I/OxAPICSide 
     */
  } Bits;
  UINT32 Data;
} MBAR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_IOAPIC_REG supported on:                                          */
/*       IVT_EP (0x2002C02C)                                                  */
/*       IVT_EX (0x2002C02C)                                                  */
/*       HSX (0x2002C02C)                                                     */
/*       BDX (0x2002C02C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIO_IOAPIC_REG 0x0904202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x02c
 */
typedef union {
  struct {
    UINT16 svid_reg : 16;
    /* svid_reg - Bits[15:0], RW_O, default = 16'b1000000010000110 
       1
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* SID_IIO_IOAPIC_REG supported on:                                           */
/*       IVT_EP (0x2002C02E)                                                  */
/*       IVT_EX (0x2002C02E)                                                  */
/*       HSX (0x2002C02E)                                                     */
/*       BDX (0x2002C02E)                                                     */
/* Register default value:              0x0000                                */
#define SID_IIO_IOAPIC_REG 0x0904202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * This value is used to identify a particular subsystem.
 */
typedef union {
  struct {
    UINT16 sid_reg : 16;
    /* sid_reg - Bits[15:0], RW_O, default = 16'b0000000000000000 
       1
     */
  } Bits;
  UINT16 Data;
} SID_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x1002C034)                                                  */
/*       IVT_EX (0x1002C034)                                                  */
/*       HSX (0x1002C034)                                                     */
/*       BDX (0x1002C034)                                                     */
/* Register default value:              0x44                                  */
#define CAPPTR_IIO_IOAPIC_REG 0x09041034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000100 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* INTLIN_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x1002C03C)                                                  */
/*       IVT_EX (0x1002C03C)                                                  */
/*       HSX (0x1002C03C)                                                     */
/*       BDX (0x1002C03C)                                                     */
/* Register default value:              0x00                                  */
#define INTLIN_IIO_IOAPIC_REG 0x0904103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x03c
 */
typedef union {
  struct {
    UINT8 intlin_reg : 8;
    /* intlin_reg - Bits[7:0], RO, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} INTLIN_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x1002C03D)                                                  */
/*       IVT_EX (0x1002C03D)                                                  */
/*       HSX (0x1002C03D)                                                     */
/*       BDX (0x1002C03D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_IOAPIC_REG 0x0904103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x03d
 */
typedef union {
  struct {
    UINT8 intpin_reg : 8;
    /* intpin_reg - Bits[7:0], RO, default = 8'b00000000 
       1
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* ABAR_IIO_IOAPIC_REG supported on:                                          */
/*       IVT_EP (0x2002C040)                                                  */
/*       IVT_EX (0x2002C040)                                                  */
/*       HSX (0x2002C040)                                                     */
/*       BDX (0x2002C040)                                                     */
/* Register default value:              0x0000                                */
#define ABAR_IIO_IOAPIC_REG 0x09042040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x040
 */
typedef union {
  struct {
    UINT16 base_address_11 : 4;
    /* base_address_11 - Bits[3:0], RW, default = 4'b0000 
       8] (ZBAD)These bits determine the low order bits of the I/O APIC address map. 
       When a memory address is recognized by the IIO which matches 
       FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
       internal I/O APIC. 
     */
    UINT16 base_address_15 : 4;
    /* base_address_15 - Bits[7:4], RW, default = 4'b0000 
       12] (YBAD)These bits determine the low order bits of the I/O APIC address map. 
       When a memory address is recognized by the IIO which matches 
       FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
       internal I/O APIC. 
     */
    UINT16 base_address_19 : 4;
    /* base_address_19 - Bits[11:8], RW, default = 4'b0000 
       16] (XBAD)These bits determine the high order bits of the I/O APIC address map. 
       When a memory address is recognized by the IIO which matches 
       FECX_YZ00-to-FECX_YZFF, the IIO will respond to the cycle and access the 
       internal I/O APIC. 
     */
    UINT16 rsvd : 3;
    /* rsvd - Bits[14:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 abar_enable : 1;
    /* abar_enable - Bits[15:15], RW, default = 1'b0 
       When set, the range FECX_YZ00 to FECX_YZFF is enabled as an alternate access 
       method to the IOxAPIC registers and these addresses are claimed by the IIO's 
       internal I/OxAPIC regardless of the setting the MSE bit in the I/OxAPIC config 
       space. Bits 'XYZ' are defined below.Side 
     */
  } Bits;
  UINT16 Data;
} ABAR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x4002C044)                                                  */
/*       IVT_EX (0x4002C044)                                                  */
/*       HSX (0x4002C044)                                                     */
/*       BDX (0x4002C044)                                                     */
/* Register default value:              0x0091E010                            */
#define PXPCAP_IIO_IOAPIC_REG 0x09044044
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x044
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b11100000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0001 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
       
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0  */
    UINT32 interrupt_message_numnber : 5;
    /* interrupt_message_numnber - Bits[29:25], RO, default = 5'b00000 
       1
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* SNAPSHOT_INDEX_IIO_IOAPIC_REG supported on:                                */
/*       IVT_EP (0x1002C080)                                                  */
/*       IVT_EX (0x1002C080)                                                  */
/*       HSX (0x1002C080)                                                     */
/*       BDX (0x1002C080)                                                     */
/* Register default value:              0x00                                  */
#define SNAPSHOT_INDEX_IIO_IOAPIC_REG 0x09041080
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * Alternate Index to read Indirect I/OxAPIC Registers
 */
typedef union {
  struct {
    UINT8 ssidx : 8;
    /* ssidx - Bits[7:0], RW, default = 8'b00000000 
       When PECI/JTAG wants to read the indirect RTE registers of I/OxAPIC, this 
       register is used to point to the index of the indirect register, as defined in 
       the I/ OxAPIC indirect memory space. Software writes to this register and then 
       does a read of the RDWINDOW register to read the contents at that index. Note 
       h/w does not preclude software from accessing this register over the coherent 
       interface but that is not what this register is defined for. 
     */
  } Bits;
  UINT8 Data;
} SNAPSHOT_INDEX_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* SNAPSHOT_WINDOW_IIO_IOAPIC_REG supported on:                               */
/*       IVT_EP (0x4002C090)                                                  */
/*       IVT_EX (0x4002C090)                                                  */
/*       HSX (0x4002C090)                                                     */
/*       BDX (0x4002C090)                                                     */
/* Register default value:              0x00000000                            */
#define SNAPSHOT_WINDOW_IIO_IOAPIC_REG 0x09044090
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * Alternate Window to read Indirect I/OxAPIC Registers
 */
typedef union {
  struct {
    UINT32 sswindow : 32;
    /* sswindow - Bits[31:0], RO_V, default = 32'b00000000000000000000000000000000 
       When SMBUS/JTAG reads this register, the data contained in the indirect register 
       pointed to by the RDINDEX register is returned on the read. 
     */
  } Bits;
  UINT32 Data;
} SNAPSHOT_WINDOW_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOAPICTETPC_IIO_IOAPIC_REG supported on:                                   */
/*       IVT_EP (0x4002C0A0)                                                  */
/*       IVT_EX (0x4002C0A0)                                                  */
/*       HSX (0x4002C0A0)                                                     */
/*       BDX (0x4002C0A0)                                                     */
/* Register default value:              0x00000000                            */
#define IOAPICTETPC_IIO_IOAPIC_REG 0x090440A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * IOxAPIC Table Entry Target Programmable Control
 */
typedef union {
  struct {
    UINT32 port0_intb : 1;
    /* port0_intb - Bits[0:0], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 1
       1: src/int is connected to IOAPIC table entry 3
       
     */
    UINT32 rsvd_1 : 3;
    /* rsvd_1 - Bits[3:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port2a_intb : 1;
    /* port2a_intb - Bits[4:4], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 12
       1: src/int is connected to IOAPIC table entry 9
       
     */
    UINT32 rsvd_5 : 1;
    /* rsvd_5 - Bits[5:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port2c_intb : 1;
    /* port2c_intb - Bits[6:6], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 13
       1: src/int is connected to IOAPIC table entry 11
       
     */
    UINT32 rsvd_7 : 1;
    /* rsvd_7 - Bits[7:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port3a_intb : 1;
    /* port3a_intb - Bits[8:8], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 20
       1: src/int is connected to IOAPIC table entry 17
       
     */
    UINT32 rsvd_9 : 1;
    /* rsvd_9 - Bits[9:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port3c_intb : 1;
    /* port3c_intb - Bits[10:10], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 21
       1: src/int is connected to IOAPIC table entry 19
       
     */
    UINT32 rsvd_11 : 1;
    /* rsvd_11 - Bits[11:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ntb_int : 1;
    /* ntb_int - Bits[12:12], RW, default = 1'b0 
       0: src/int is connected to IOAPIC table entry 16
       1: src/int is connected to IOAPIC table entry 23
       NTB interrupt is always mapped to entry 23.
     */
    UINT32 rsvd_13 : 3;
    /* rsvd_13 - Bits[15:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rsvd_16 : 1;
    UINT32 rsvd_17 : 15;
    /* rsvd_17 - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IOAPICTETPC_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* PMCAP_IIO_IOAPIC_REG supported on:                                         */
/*       IVT_EP (0x4002C0E0)                                                  */
/*       IVT_EX (0x4002C0E0)                                                  */
/*       HSX (0x4002C0E0)                                                     */
/*       BDX (0x4002C0E0)                                                     */
/* Register default value:              0x00030001                            */
#define PMCAP_IIO_IOAPIC_REG 0x090440E0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x0e0
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00000001 
       Provides the PM capability ID assigned by PCI-SIG.
     */
    UINT32 next_pointer : 8;
    /* next_pointer - Bits[15:8], RO, default = 8'b00000000  */
    UINT32 version : 3;
    /* version - Bits[18:16], RW_O, default = 3'b011 
       This field is set to 3h (PM 1.2 compliant) as version number.
     */
    UINT32 pme_clock : 1;
    /* pme_clock - Bits[19:19], RO, default = 1'b0  */
    UINT32 rsvd : 1;
    /* rsvd - Bits[20:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 device_specific_initalization : 1;
    /* device_specific_initalization - Bits[21:21], RO, default = 1'b0  */
    UINT32 aux_current : 3;
    /* aux_current - Bits[24:22], RO, default = 3'b000  */
    UINT32 d1_support : 1;
    /* d1_support - Bits[25:25], RO, default = 1'b0  */
    UINT32 d2_support : 1;
    /* d2_support - Bits[26:26], RO, default = 1'b0  */
    UINT32 pme_support : 5;
    /* pme_support - Bits[31:27], RO, default = 5'b00000 
       Bits 31, 30 and 27 must be set to \q1\q for PCI-PCI bridge structures 
       representing ports on root complexes. 
     */
  } Bits;
  UINT32 Data;
} PMCAP_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* PMCSR_IIO_IOAPIC_REG supported on:                                         */
/*       IVT_EP (0x4002C0E4)                                                  */
/*       IVT_EX (0x4002C0E4)                                                  */
/*       HSX (0x4002C0E4)                                                     */
/*       BDX (0x4002C0E4)                                                     */
/* Register default value:              0x00000008                            */
#define PMCSR_IIO_IOAPIC_REG 0x090440E4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x0e4
 */
typedef union {
  struct {
    UINT32 power_state : 2;
    /* power_state - Bits[1:0], RW_V, default = 2'b00 
       This 2-bit field is used to determine the current power state of the function 
       and to set a new power state as well. 
       00: D0
       01: D1 (not supported by IOAPIC)
       10: D2 (not supported by IOAPIC)
       11: D3_hot
       If Software tries to write 01 or 10 to this field, the power state does not 
       change from the existing power state (which is either D0 or D3hot) and nor do 
       these bits1:0 change value. 
       When in D3hot state, I/OxAPIC will
       a) respond to only Type 0 configuration transactions targeted at the device's 
       configuration space, when in D3hot state 
       c) will not respond to memory (i.e. D3hot state is equivalent to MSE ), accesses 
       to MBAR region (note: ABAR region access still go through in D3hot state, if it 
       enabled) 
       d) will not generate any MSI writes
     */
    UINT32 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rstd3hotd0 : 1;
    /* rstd3hotd0 - Bits[3:3], RO, default = 1'b1  */
    UINT32 rsvd_4 : 4;
    /* rsvd_4 - Bits[7:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 pmeen : 1;
    /* pmeen - Bits[8:8], RO, default = 1'b0  */
    UINT32 dsel : 4;
    /* dsel - Bits[12:9], RO, default = 4'b0000  */
    UINT32 dscl : 2;
    /* dscl - Bits[14:13], RO, default = 2'b00  */
    UINT32 pmests : 1;
    /* pmests - Bits[15:15], RO, default = 1'b0  */
    UINT32 rsvd_16 : 6;
    /* rsvd_16 - Bits[21:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 b2b3 : 1;
    /* b2b3 - Bits[22:22], RO, default = 1'b0  */
    UINT32 bpcce : 1;
    /* bpcce - Bits[23:23], RO, default = 1'b0  */
    UINT32 data : 8;
    /* data - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} PMCSR_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOADSELS0_IIO_IOAPIC_REG supported on:                                     */
/*       IVT_EP (0x4002C288)                                                  */
/*       IVT_EX (0x4002C288)                                                  */
/*       HSX (0x4002C288)                                                     */
/*       BDX (0x4002C288)                                                     */
/* Register default value:              0x00000000                            */
#define IOADSELS0_IIO_IOAPIC_REG 0x09044288


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x288
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 27;
    /* rsvd_0 - Bits[26:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 sw2ipc_aer_event_sel : 1;
    /* sw2ipc_aer_event_sel - Bits[27:27], RWS, default = 1'b0  */
    UINT32 sw2ipc_aer_negedge_msk : 1;
    /* sw2ipc_aer_negedge_msk - Bits[28:28], RWS, default = 1'b0  */
    UINT32 rsvd_29 : 3;
    /* rsvd_29 - Bits[31:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IOADSELS0_IIO_IOAPIC_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* IOINTSRC0_IIO_IOAPIC_REG supported on:                                     */
/*       IVT_EP (0x4002C2A0)                                                  */
/*       IVT_EX (0x4002C2A0)                                                  */
/*       HSX (0x4002C2A0)                                                     */
/*       BDX (0x4002C2A0)                                                     */
/* Register default value:              0x00000000                            */
#define IOINTSRC0_IIO_IOAPIC_REG 0x090442A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * IO Interrupt Source Register 0
 */
typedef union {
  struct {
    UINT32 int_src0 : 32;
    /* int_src0 - Bits[31:0], RW_V, default = 32'b00000000000000000000000000000000 
       
       bit interrupt source
       31: INTD Port 3b
       30: INTC Port 3b
       29: INTB Port 3b
       28: INTA Port 3b
       27: INTD Port 3a
       26: INTC Port 3a
       25: INTB Port 3a
       24: INTA Port 3a
       23: INTD Port 1b
       22: INTC Port 1b
       21: INTB Port 1b
       20: INTA Port 1b
       19: INTD Port 1a
       18: INTC Port 1a
       17: INTB Port 1a
       16: INTA Port 1a
       15: INTD Port 2d
       14: INTC Port 2d
       13: INTB Port 2d
       12: INTA Port 2d
       11: INTD Port 2c
       10: INTC Port 2c
       9: INTB Port 2c
       8: INTA Port 2c
       7: INTD Port 2b
       6: INTC Port 2b
       5: INTB Port 2b
       4: INTA Port 2b
       3: INTD Port 2a
       2: INTC Port 2a
       1: INTB Port 2a
       0: INTA Port 2a
     */
  } Bits;
  UINT32 Data;
} IOINTSRC0_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOINTSRC1_IIO_IOAPIC_REG supported on:                                     */
/*       IVT_EP (0x4002C2A4)                                                  */
/*       IVT_EX (0x4002C2A4)                                                  */
/*       HSX (0x4002C2A4)                                                     */
/*       BDX (0x4002C2A4)                                                     */
/* Register default value:              0x00000000                            */
#define IOINTSRC1_IIO_IOAPIC_REG 0x090442A4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * IO Interrupt Source Register 1
 */
typedef union {
  struct {
    UINT32 int_src1 : 21;
    /* int_src1 - Bits[20:0], RW_V, default = 21'b000000000000000000000 
       
       bit interrupt source
       20: INTA Root Port Core
       19: INTB ME KT
       18: INTC ME IDE-R
       17: INTD ME HECI
       16: INTA ME HECI
       15: INTD CB DMA
       14: INTC CB DMA
       13: INTB CB DMA
       12: INTA CB DMA
       11: INTD Port 0/DMI
       10: INTC Port 0/DMI
       9: INTB Port 0/DMI
       8: INTA Port 0/DMI
       7: INTD Port 3d
       6: INTC Port 3d
       5: INTB Port 3d
       4: INTA Port 3d
       3: INTD Port 3c
       2: INTC Port 3c
       1: INTB Port 3c
       0: INTA Port 3c
     */
    UINT32 rsvd : 11;
    /* rsvd - Bits[31:21], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IOINTSRC1_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOREMINTCNT_IIO_IOAPIC_REG supported on:                                   */
/*       IVT_EP (0x4002C2A8)                                                  */
/*       IVT_EX (0x4002C2A8)                                                  */
/*       HSX (0x4002C2A8)                                                     */
/*       BDX (0x4002C2A8)                                                     */
/* Register default value:              0x00000000                            */
#define IOREMINTCNT_IIO_IOAPIC_REG 0x090442A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * Remote IO Interupt Count
 */
typedef union {
  struct {
    UINT32 rem_int_cnt : 32;
    /* rem_int_cnt - Bits[31:0], RW_V, default = 32'b00000000000000000000000000000000 
       Number of remote interrupts received.
     */
  } Bits;
  UINT32 Data;
} IOREMINTCNT_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOREMGPECNT_IIO_IOAPIC_REG supported on:                                   */
/*       IVT_EP (0x4002C2AC)                                                  */
/*       IVT_EX (0x4002C2AC)                                                  */
/*       HSX (0x4002C2AC)                                                     */
/*       BDX (0x4002C2AC)                                                     */
/* Register default value:              0x00000000                            */
#define IOREMGPECNT_IIO_IOAPIC_REG 0x090442AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * Remote IO GPE Count
 */
typedef union {
  struct {
    UINT32 gpe_cnt : 8;
    /* gpe_cnt - Bits[7:0], RW_V, default = 8'b00000000 
       Number of remote GPEs received.
     */
    UINT32 pmgpe_cnt : 8;
    /* pmgpe_cnt - Bits[15:8], RW_V, default = 8'b00000000 
       Number of remote PMGPEs received.
     */
    UINT32 hpgpe_cnt : 8;
    /* hpgpe_cnt - Bits[23:16], RW_V, default = 8'b00000000 
       Number of remote HPGPEs received.
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IOREMGPECNT_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOXAPICPARERRINJCTL_IIO_IOAPIC_REG supported on:                           */
/*       IVT_EP (0x4002C2C0)                                                  */
/*       IVT_EX (0x4002C2C0)                                                  */
/*       HSX (0x4002C2C0)                                                     */
/*       BDX (0x4002C2C0)                                                     */
/* Register default value:              0x00000000                            */
#define IOXAPICPARERRINJCTL_IIO_IOAPIC_REG 0x090442C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * generated by critter 05_4_0x2c0
 */
typedef union {
  struct {
    UINT32 pf : 4;
    /* pf - Bits[3:0], RWS_L, default = 4'b0000 
       pf[3:0]
     */
    UINT32 rsvd_4 : 14;
    /* rsvd_4 - Bits[17:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 notused : 4;
    /* notused - Bits[21:18], RWS_L, default = 4'b0000 
       1
     */
    UINT32 rsvd_22 : 2;
    /* rsvd_22 - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 bfs : 2;
    /* bfs - Bits[25:24], RWS_L, default = 2'b00 
       bfs[1:0]
     */
    UINT32 rsvd_26 : 4;
    /* rsvd_26 - Bits[29:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 eirfs : 1;
    /* eirfs - Bits[30:30], RWS_L, default = 1'b0  */
    UINT32 eie : 1;
    /* eie - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} IOXAPICPARERRINJCTL_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* FAUXGV_IIO_IOAPIC_REG supported on:                                        */
/*       IVT_EP (0x4002C2C4)                                                  */
/*       IVT_EX (0x4002C2C4)                                                  */
/*       HSX (0x4002C2C4)                                                     */
/*       BDX (0x4002C2C4)                                                     */
/* Register default value:              0x00000000                            */
#define FAUXGV_IIO_IOAPIC_REG 0x090442C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.5.4.CFG.xml.
 * FauxGV enable
 */
typedef union {
  struct {
    UINT32 fauxgven : 1;
    /* fauxgven - Bits[0:0], RWS_L, default = 1'b0 
       Enable Fault GV.
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} FAUXGV_IIO_IOAPIC_STRUCT;
#endif /* ASM_INC */


/* IOADSELS1_IIO_IOAPIC_REG supported on:                                     */
/*       IVT_EP (0x4002C28C)                                                  */
/*       IVT_EX (0x4002C28C)                                                  */
/* Register default value:              0x00000000                            */
#define IOADSELS1_IIO_IOAPIC_REG 0x0904428C



#endif /* IIO_IOAPIC_h */
